Dual-phase delay-locked loop circuit and method

ABSTRACT

A delay-locked loop includes a clock multiplier that generates a multiplied clock signal responsive to an input clock signal. The multiplied clock signal has a frequency that is a multiple of a frequency of the input clock signal. A variable delay circuit generates a delayed clock signal responsive to the multiplied clock signal, the delayed clock signal having a delay relative to the multiplied clock signal. The variable delay circuit controls the value of the delay responsive to a delay control signal. A comparison circuit generates the delay control signal in response to the relative phases of the delayed clock signal and the multiplied clock signal. In another embodiment, the delay-locked loop omits the clock multiplier and instead includes a comparison circuit that generates the delay control signal in response to the relative phases of both the rising- and falling-edge transitions of the delayed and input clock signals.

TECHNICAL FIELD

[0001] The present invention relates generally to integrated circuits,and more specifically to synchronizing an external clock signal appliedto an integrated circuit with internal clock signals generated in theintegrated circuit in response to the external clock signal.

BACKGROUND OF THE INVENTION

[0002] In synchronous integrated circuits, the integrated circuit isclocked by an external clock signal and performs operations atpredetermined times relative the rising and falling edges of the appliedclock signal. Examples of synchronous integrated circuits includesynchronous memory devices such as synchronous dynamic random accessmemories (SDRAMs), synchronous static random access memories (SSRAMs),and packetized memories like SLDRAMs and RDRAMs, and include other typesof integrated circuits as well, such as microprocessors. The timing ofsignals external to a synchronous memory device is determined by theexternal clock signal, and operations within the memory device typicallymust be synchronized to external operations. For example, commands areplaced on a command bus of the memory device in synchronism with theexternal clock signal, and the memory device must latch these commandsat the proper times to successfully capture the commands. To latch theapplied commands, an internal clock signal is developed in response tothe external clock signal, and is typically applied to latches containedin the memory device to thereby clock the commands into the latches. Theinternal clock signal and external clock must be synchronized to ensurethe internal clock signal clocks the latches at the proper times tosuccessfully capture the commands. In the present description,“external” is used to refer to signals and operations outside of thememory device, and “internal” to refer to signals and operations withinthe memory device. Moreover, although the present description isdirected to synchronous memory devices, the principles described hereinare equally applicable to other types of synchronous integratedcircuits.

[0003] Internal circuitry in the memory device that generates theinternal clock signal necessarily introduces some time delay, causingthe internal clock signal to be phase shifted relative to the externalclock signal. As long as the phase-shift is minimal, timing within thememory device can be easily synchronized to the external timing. Toincrease the rate at which commands can be applied and at which data canbe transferred to and from the memory device, the frequency of theexternal clock signal is increased, and in modern synchronous memoriesthe frequency is in excess of 100 MHZ. As the frequency of the externalclock signal increases, however, the time delay introduced by theinternal circuitry becomes more significant. This is true because as thefrequency of the external clock signal increases, the period of thesignal decreases and thus even small delays introduced by the internalcircuitry correspond to significant phase shifts between the internaland external clock signals. As a result, the commands applied to thememory device may no longer be valid by the time the internal clocksignal clocks the latches.

[0004] To synchronize external and internal clock signals in modemsynchronous memory devices, a number of different approaches have beenconsidered and utilized, including delay-locked loops (DLLs),phased-locked loops (PLLs), and synchronous mirror delays (SMDs), aswill be appreciated by those skilled in the art. As used herein, theterm synchronized includes signals that are coincident and signals thathave a desired delay relative to one another. FIG. 1 is a functionalblock diagram illustrating a conventional delay-locked loop 100including a variable delay line 102 that receives a clock buffer signalCLKBUF and generates a delayed clock signal CLKDEL in response to theclock buffer signal. The variable delay line 102 controls a variabledelay VD of the CLKDEL signal relative to the CLKBUF signal in responseto a delay adjustment signal DADJ. A feedback delay line 104 generates afeedback clock signal CLKFB in response to the CLKDEL signal, thefeedback clock signal having a model delay D1+D2 relative to the CLKDELsignal. The D1 component of the model delay D1+D2 corresponds to a delayintroduced by an input buffer 106 that generates the CLKBUF signal inresponse to an external clock signal CLK, while the D2 component of themodel delay corresponds to a delay introduced by an output buffer 108that generates a synchronized clock signal CLKSYNC in response to theCLKDEL signal. Although the input buffer 106 and output buffer 108 areillustrated as single components, each represents all components and theassociated delay between the input and output of the delay-locked loop100. The input buffer 106 thus represents the delay D1 of all componentsbetween an input that receives the CLK signal and the input to thevariable delay line 102, and the output buffer 108 represents the delayD2 of all components between the output of the variable delay line andan output at which the CLKSYNC signal is developed.

[0005] The delay-locked loop 100 further includes a phase detector 110that receives the CLKFB and CLKBUF signals and generates a delay controlsignal DCONT having a value indicating the phase difference between theCLKBUF and CLKFB signals. One implementation of a phase detector isdescribed in U.S. Pat. No. 5,946,244 to Manning (Manning), which isassigned to the assignee of the present patent application and which isincorporated herein by reference. A delay controller 112 generates theDADJ signal in response to the DCONT signal from the phase detector 110,and applies the DADJ signal to the variable delay line 102 to adjust thevariable delay VD. The phase detector 110 and delay controller 112operate in combination to adjust the variable delay VD of the variabledelay line 102 as a function of the detected phase between the CLKBUFand CLKFB signals.

[0006] In operation, the phase detector 110 detects the phase differencebetween the CLKBUF and CLKFB signals, and the phase detector and delaycontroller 112 operate in combination to adjust the variable delay VD ofthe CLKDEL signal until the phase difference between the CLKBUF andCLKFB signals is approximately zero. More specifically, as the variabledelay VD of the CLKDEL signal is adjusted the phase of the CLKFB signalfrom the feedback delay line 104 is adjusted accordingly until the CLKFBsignal has approximately the same phase as the CLKBUF signal. When thedelay-locked loop 100 has adjusted the variable delay VD to a valuecausing the phase shift between the CLKBUF and CLKFB signals to equalapproximately zero, the delay-locked loop is said to be “locked.” Whenthe delay-locked loop 100 is locked, the CLK and CLKSYNC signals aresynchronized. This is true because when the phase shift between theCLKBUF and CLKFB signals is approximately zero (i.e., the delay-lockedloop 100 is locked), the variable delay VD has a value of NTCK−(D1+D2)as indicated in FIG. 1, where N is an integer and TCK is the period ofthe CLK signal. When VD equals NTCK-(D1+D2), the total delay of the CLKsignal through the input buffer 106, variable delay line 102, and outputbuffer 108 is D1+NTCK−(D1+D2)+D2, which equals NTCK. Thus, the CLKSYNCsignal is delayed by NTCK relative to the CLK signal and the two signalsare synchronized since the delay is an integer multiple of the period ofthe CLK signal. Referring back to the discussion of synchronous memorydevices above, the CLK signal corresponds to the external clock signaland the CLKSYNC signal corresponds to the internal clock signal.

[0007]FIG. 2 is a signal timing diagram illustrating various signalsgenerated during operation of the delay-locked loop 100 of FIG. 1. Inresponse to a rising-edge of the CLK signal at a time TO, the CLKBUFsignal goes high the delay D1 later at a time T1. Initially, thevariable delay VD as a value VD1, causing the CLKDEL signal to go highat a time T3 and the CLKSYNC signal to go high at a time T4. At thispoint, note that the positive-edge of the CLKSYNC signal at the time T4is not synchronized with the CLK signal, which transitions high at atime T5. In response to the rising-edge of the CLKDEL signal at the timeT3, the CLKFB goes high at a time T6, which occurs before apositive-edge of the CLKBUF signal occurring at a time T7. Thus, thepositive-edge of the CLKFB signal occurs at the time T6 while thepositive-edge of the CLKBUF occurs at the time T7, indicating there is aphase shift between the two signals. The phase detector 110 (FIG. 1)detects this phase difference, and generates the DCONT signal just afterthe time T7 at a time T8 which, in turn, causes the delay controller 112(FIG. 1) to generate the DADJ signal to adjust the value of the variabledelay VD to a new value VD2.

[0008] In response to the new variable delay VD2, the next rising-edgeof the CLKDEL signal occurs at a time T9. The CLKSYNC signal transitionshigh the delay D2 later at a time T10 and in synchronism with arising-edge of the CLK signal. At this point, the delay-locked loop 100is locked. In response to the positive-edge transition of the CLKDELsignal at the time T9, the CLKFB signal transitions high at a time T11in synchronism with the CLKBUF signal. Once again, the phase detector110 (FIG. 1) detects the phase difference between the CLKBUF and CLKFBsignals, which in this case is approximately zero, and generates theDCONT signal just after the time T11 in response to the detected phasedifference. In this situation, the generated DCONT signal would notcause the variable delay VD2 to be adjusted since the delay-locked loop100 is locked. Moreover, although the relative phases of the CLKBUF andCLKFB signals is detected in response to each rising-edge of thesesignals, the variable delay VD may not be adjusted immediately evenwhere such a phase difference is detected. For example, the variabledelay VD may be adjusted only when a phase difference between the CLKFBand CLKBUF signals exists for a predetermined time or exceeds apredetermined magnitude. In this way, the phase detector 110 and delaycontroller 112 can provide a sort of “filtering” of jitter or variationsin the CLK signal, as will be understood in the art.

[0009] In the delay-locked loop 100, each cycle of the CLK signal thephase detector 110 compares rising-edges of the CLKBUF and CLKFB signalsand generates the appropriate DCONT signal to incrementally adjust thevariable delay VD until the delay-locked loop 100 is locked. The phasedetector 110 could also compare falling-edges of the CLKBUF and CLKFBsignals, as in the previously mentioned Manning patent. In this way, thedelay-locked loop 100 incrementally adjusts the variable delay VD onceeach cycle of the CLK signal. Although the example of FIG. 2 illustratesthe delay-locked loop 100 as locking and therefore synchronizing the CLKand CLKSYNC signals after only two cycles of the CLK signal, thedelay-locked loop typically takes as many as 200 cycles of the CLKsignal to lock. Before the delay-locked loop 100 is locked, the CLKSYNCsignal cannot be used to latch signals being applied to the synchronousmemory device containing the delay-locked loop. As a result, the time ittakes to lock the delay-locked loop 100 may slow the operation of theassociated synchronous memory device. For example, in a conventionaldouble data rate (DDR) SDRAM, the delay-locked loop is automaticallydisabled when the SDRAM enters a self-refresh mode of operation. Uponexiting the self-refresh mode, 200 cycles of the applied CLK signal mustthen occur before read or write data transfer commands can be applied tothe SDRAM.

[0010] In the delay-locked loop 100, the variable delay line 102typically is formed from a number of serially-connected individual delaystages, with individual delay stages being added or removed to adjustthe variable delay VD, as will be understood by those skilled in theart. For example, a plurality of serially-connected inverters could beused to form the variable delay line 102, with the output from differentinverters being selected in response to the DADJ to control the variabledelay VD. A large number of stages in the variable delay line 102 isdesirable with each stage having an incremental delay to provide betterresolution in controlling the value of the variable delay VD. Inaddition, the variable delay line 102 must be able to provide themaximum variable delay VD corresponding to the CLK signal having thelowest frequency in the frequency range over which the delay-locked loopis designed to operate. This is true because the variable delay line 102must provide a variable delay VD of NTCK−(D1+D2), which will have itslargest value when the period of the CLK signal is greatest, whichoccurs at the lowest frequency of the CLK signal. The desired fineresolution and maximum variable delay VD that the variable delay line102 must provide can result in the delay line consisting of a largenumber of individual delay stages that consume a relatively large amountof space on a semiconductor substrate in which the delay-locked loop 100and other components of the synchronous memory device are formed.Moreover, such a large number of individual delay stages can result insignificant power consumption by the delay-locked loop 100, which may beundesirable particularly in applications where synchronous memory deviceis contained in a portable battery-powered device.

[0011] There is a need for a delay-locked loop that occupies less spaceon a semiconductor substrate, consumes less power, and more quicklylocks on an applied clock signal.

SUMMARY OF THE INVENTION

[0012] According to one aspect of the present invention, a delay-lockedloop, includes a clock multiplier that generates a multiplied clocksignal responsive to an input clock signal. The multiplied clock signalhas a frequency that is a multiple of a frequency of the input clocksignal. A variable delay circuit is coupled to the clock multiplier andgenerates a delayed clock signal responsive to the multiplied clocksignal. The delayed clock signal has a delay relative to the multipliedclock signal and the variable delay circuit controls the value of thedelay responsive to a delay control signal. A comparison circuit iscoupled to the clock multiplier and to the variable delay circuit togenerate the delay control signal in response to the relative phases ofthe delayed clock signal and the multiplied clock signal.

[0013] According to another aspect of the present invention, adelay-locked loop includes a variable delay circuit that receives aninput clock signal and generates a delayed clock signal responsive tothe input clock signal. The delayed clock signal has a delay relative tothe input clock signal and the variable delay circuit controls the valueof the delay responsive to a delay control signal. A comparison circuitis coupled to the variable delay circuit and generates the delay controlsignal in response to the relative phases of the rising-edge transitionsof the delayed and input clock signals and in response to the relativephases of the falling-edge transitions of the delayed and input clocksignals.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014]FIG. 1 is a functional block diagram of a conventionaldelay-locked loop.

[0015]FIG. 2 is a signal timing diagram illustrating various signalsgenerated during operation of the delay-locked loop of FIG. 1.

[0016]FIG. 3 is a functional block diagram of a delay-locked loopaccording to one embodiment of the present invention.

[0017]FIG. 4 is a signal timing diagram illustrating various signalsgenerated during operation of the delay-locked loop of FIG. 3.

[0018]FIG. 5 is a functional block diagram illustrating a delay-lockedloop according to another embodiment of the present invention.

[0019]FIG. 6 is a signal timing diagram illustrating various signalsgenerated during operation of the delay-locked loop of FIG. 5.

[0020]FIG. 7 is a diagram illustrating one embodiment of the clockmultiplier of FIG. 3 and various signals generated during operation ofthe clock multiplier.

[0021]FIG. 8 is a functional block diagram illustrating a synchronousmemory device including the delay-locked loop of FIG. 3 and/or thedelay-locked loop of FIG. 5.

[0022]FIG. 9 is a functional block diagram illustrating a computersystem including a synchronous memory device of FIG. 8.

DETAILED DESCRIPTION OF THE INVENTION

[0023]FIG. 3 is a functional block diagram of a delay-locked loop 300including a clock multiplier 302 that multiplies a frequency of anapplied external clock signal CLK, allowing a variable delay VD of adelayed clock signal CLKDEL to be adjusted multiple times during eachcycle of the applied clock signal and thereby enabling the applied clocksignal to be more quickly locked, as will be explained in more detailbelow. In addition to locking more quickly on the CLK signal, thedelay-locked loop 300 also enables a smaller variable delay line 304 tobe utilized over a given operating frequency range due to the increasedfrequency of the signal being locked, as will also be explained below inmore detail. In the following description, certain details are set forthto provide a sufficient understanding of the invention. It will be clearto one skilled in the art, however, that the invention may be practicedwithout these particular details. In other instances, well-knowncircuits, control signals, timing protocols, and software operationshave not been shown in detail or omitted entirely in order to avoidunnecessarily obscuring the invention.

[0024] The delay-locked loop 300 includes the variable delay line 304, afeedback delay line 306, a phase detector 308, and a delay controller310, all of which operate individually and in combination as previouslydescribed for the corresponding components in the conventionaldelay-locked loop 100 of FIG. 1. Thus, for the sake of brevity, theoperation of these components will not again be described in detail. Inthe delay-locked loop 300, the clock multiplier 302 generates amultiplied clock signal MCLK in response to the CLK signal. The MCLKsignal has a frequency FMCLK equal to a frequency FCLK of the CLK signaltimes 2^ N, where N is an integer (i.e., FMCLK=FCLK×2^ N). In theembodiment of FIG. 3, N=1 so that the frequency FMCLK of the MCLK signalis twice the frequency FCLK of the CLK signal.

[0025] An input buffer 310 develops a clock buffer signal CLKBUF inresponse to the MCLK signal. The input buffer 310 introduces an inputbuffer delay DIB, causing the CLKBUF signal to be delayed by the inputbuffer delay relative to the MCLK signal. The clock multiplier 302 alsointroduces a delay to the MCLK signal relative to the CLK signal. Thedelay introduced by the clock multiplier 302 plus the input buffer delayDIB introduced by the input buffer 310 together form the model delaycomponent D1 in the feedback delay line 306. Although the clockmultiplier 302 is shown connected before the input buffer 310 in theembodiment of FIG. 3, one skilled in the art will realize the inputbuffer and clock multiplier would typically be reversed, with the inputbuffer receiving the CLK signal and supplying the CLKBUF signal to theclock multiplier which, in turn, applies the MCLK signal to the variabledelay line 304.

[0026] In the delay-locked loop 300, a clock divider 312 receives theCLKDEL signal and generates a divided clock signal DVCLK having thefrequency FCLK of the CLKDEL signal. Thus, in the embodiment of FIG. 3,the clock divider 312 divides the multiplied frequency FMCLK of the MCLKsignal by two to generate the DVCLK signal having the same frequency asthe CLK. The clock divider 312 could also divide the frequency of theCLKDEL signal by other factors to generate the DVCLK signal having afrequency that is equal to the FMCLK signal divided by 2^ N. A phasedetection and correction circuit 314 receives the DVCLK and CLK signals,detects whether these two signals are approximately 180 degrees out ofphase, and generates a corrected divided clock signal CDVCLK in responseto the detected phase. More specifically, when the phase detection andcorrection circuit 314 determines the DVCLK and CLK signals are notapproximately 180 degrees out of phase, the circuit outputs the DVCLK asthe CDVCLK signal. In contrast, when the phase detection and correctioncircuit 314 detects the phase between the DVCLK and CLK signals isapproximately 180 degrees, the phase detection and correction circuitinverts the DVCLK signal to generate the CDVCLK signal. The phasedetection and correction circuit 314 prevents the delay-locked loop 300from generating an output signal that is 180 degrees out of phase withthe CLK signal, which can occur when the total delay introduced by thedelay-locked loop equals one-half the period TCK of the CLK signal, aswill be appreciated by those skilled in the art.

[0027] An output buffer 316 generates a synchronized clock signalCLKSYNC signal in response to the CDVCLK signal, the CLKSYNC beingsynchronized with the CLK signal. The output buffer 316 introduces anoutput buffer delay DOB, causing the CLKSYNC signal to be delayed bythis amount relative to the CDVCLK signal. The output buffer delay DOB,along with delays introduced by the clock divider 312 and phasedetection and correction circuit 314, form the D2 component of the modeldelay D1+D2 generated by the feedback delay line 306. As illustrated bya dotted line in FIG. 3, the output buffer 316 may correspond to a datadriver that receives a data signal DQX and outputs the data signal inresponse to being clocked by the CDVCLK signal, as will be appreciatedby those skilled in the art. One skilled in the art will understandvarious circuits that may be utilized to form the components 302-316 ofthe delay-locked loop 300.

[0028] The operation of the delay-locked loop 300 will now be brieflydescribed with reference to the signal timing diagram of FIG. 4 thatillustrates various signals generated in the delay-locked loop duringoperation. The detailed operation of the delay-locked loop 300 issimilar to that previously described for the delay-locked loop 100 ofFIG. 1, and thus, for the sake of brevity, a detailed description willnot again be provided. In the delay-locked loop 300, the MCLK, CLKBUF,CLKDEL, and CLKFB signals are all twice the frequency of the CLK signal.Note that each rising-edge and falling-edge transition of the CLK signalgenerates a corresponding rising-edge of the MCLK signal, as shown attimes T1, T2 and at times T3, T4, and that each rising-edge of the MCLKsignal generates a corresponding rising-edge of the CLKBUF signal, asshown at times T5, T6. As previously described, the phase detector 308(FIG. 3) compares each rising-edge of the CLKBUF signal to acorresponding rising-edge of the CLKFB signal, as illustrated at timesT7, T8, and T9. Because the frequency of the CLKBUF and CLKFB signals istwice the frequency of the CLK signal, these comparisons occur twiceduring each period of the CLK signal. For example, for the period TCK ofthe CLK signal extending from a time T10 to a time T11, the phasedetector 308 asserts the delay control signal DCONT signal twice at thetimes T7 and the T8.

[0029] The delay-locked loop 300 adjusts the delay of the CLKDEL signalin response to both rising- and falling-edges of the CLK signal,enabling the delay-locked to more quickly lock the CLK and CLKSYNCsignals. This is true because the delay-locked loop 300 adjusts thephase of CLKDEL signal more frequently (twice per period TCK of the CLKsignal) to thereby lock the CLK and CLKSYNC signals. Moreover, since thefrequency of the CLKBUF, CLKDEL, and CLKFB signals is twice thefrequency FCLK of the CLK signal, the variable delay line 304 (FIG. 3)may be smaller than a conventional variable delay line. The maximumvariable delay VD the variable delay line 304 must provide is given byN×TCK−(D1+D2) for the maximum period TCK of the CLK signal to be locked,and in the delay-locked loop 300 the maximum period TCK is one-half themaximum period of the corresponding CLK signal due to the frequency ofthe CLKBUF, CLKDEL, and CLKFB signals being doubled.

[0030]FIG. 5 is a functional block diagram of a delay-locked loop 500that adjusts a delay of a synchronized clock signal CLKSYNC relative toan applied clock signal CLK in response to both rising- andfalling-edges of the applied clock signal according to anotherembodiment of the present invention. The delay-locked loop 500 includesa variable delay line 502, a feedback delay line 504, an input buffer506, and an output buffer 508, all of which operate as previouslydescribed for the corresponding components in the delay-locked loop 300of FIG. 3, and thus, for the sake of brevity, the operation of thesecomponents will not again be described in detail. The delay-locked loop500 further includes a rising-edge phase detector 510 that receives theCLKFB and CLKBUF signals and generates a rising-edge delay controlsignal RDCONT having a value indicating the phase difference betweenrising-edges of the CLKBUF and CLKFB signals. A falling-edge phasedetector 512 receives the CLKFB and CLKBUF signals and generates afalling-edge delay control signal FDCONT having a value indicating thephase difference between falling-edges of the CLKFB and CLKBUF signals.A delay controller 514 generates a delay adjustment signal DADJ inresponse to the RDCONT and FDCONT signals from the phase detectors 510,512, and applies the DADJ signal to the variable delay line 102 toadjust the variable delay VD. The phase detectors 510, 512 and delaycontroller 514 operate in combination to adjust the variable delay VD ofthe variable delay line 502 as a function of the detected phase betweenrising-edges and falling-edges of the CLKBUF and CLKFB signals.

[0031] In operation, the phase detector 510 detects the phase differencebetween rising-edges of the CLKBUF and CLKFB signals and applies thecorresponding RDCONT signal to the delay controller 514 which, in turn,generates the DADJ signal to adjust the variable delay VD of the CLKDELsignal. The phase detector 512 operates in the same way to detect thephase difference between falling-edges of the CLKBUF and CLKFB signalsand applied the corresponding FDCONT signal to the delay controller 514which, in turn, generates the DADJ signal to adjust the variale delay VDof the CLKDEL signal. The phase detectors 510, 512 and delay controller514 operate in combination to adjust the delay of the CLKDEL signaluntil the phase difference between the CLKBUF and CLKFB signals isapproximately zero.

[0032] The operation of the delay-locked loop 500 will now be brieflydescribed with reference to the signal timing diagram of FIG. 6, whichillustrates various signals generated in the delay-locked loop duringoperation. The detailed operation of the delay-locked loop 500 issimilar to that previously described for the delay-locked loop 300 ofFIG. 3, and thus, for the sake of brevity, a detailed description willnot again be provided. In the delay-locked loop 500, the rising-edgephase detector 510 compares rising-edges of the CLKFB and CLKBUF signalsat times T1 and T2, and generates the RDCONT signal at just after thetime T2 to adjust the variable delay VD of the CLKDEL signal in responseto the detected phase difference. Similarly, at times T3 and T4, thefalling-edge phase detector 512 compares falling-edges of the CLKFB andCLKBUF signals, and generates the FDCONT signal at just after the timeT4 to adjust the variable delay VD of the CLKDEL signal in response tothe detected phase difference. Thus, the delay-locked loop 500 adjuststhe variable delay VD of the variable delay line 502 (FIG. 5) twiceduring each period TCK of the CLK signal, once in response to therising-edge of the CLK signal and once in response to the falling-edgeof the CLK signal. In this way, the delay-locked loop 500 more quicklysynchronizes the CLK and CLKSYNC signals, reducing the number of cyclesof the CLK signal required for the delay-locked loop to lock.

[0033]FIG. 7 is a diagram illustrating one embodiment of the clockmultiplier 302 of FIG. 3 and various signals generated during operationof the clock multiplier. An XOR gate 700 receives the CLK signal on afirst input, and a delay circuit 702 receives the CLK signal and appliesa delayed signal DO to a second input of the XOR gate in response to theCLK signal. As the timing diagram of FIG. 7 illustrates, the delaycircuit 702 generates the delayed signal DO having a delay TD relativeto the either a rising- or falling-edge of the CLK signal. In operation,when the CLK transitions high or low, the XOR gate 700 receives the highor low CLK signal on one input and the complement of the CLK signal onthe other input for the delay TD. In response to these signals, the XORgate 700 drives the MCLK signal high for the delay TD, at which pointboth inputs of the XOR gate 700 receive either high or low signals,causing the XOR gate to drive the MCLK signal low.

[0034]FIG. 8 is a functional block diagram of a memory device 800including the delay-locked loop 300 of FIG. 3 and/or the delay-lockedloop 500 of FIG. 5. The memory device 800 in FIG. 8 is a double-datarate (DDR) synchronous dynamic random access memory (“SDRAM”), althoughthe principles described herein are applicable to any memory device thatmay include a delay-locked loop for synchronizing internal and externalsignals, such as conventional synchronous DRAMs (SDRAMs), as well aspacketized memory devices like SLDRAMs and RDRAMs, and are equallyapplicable to any integrated circuit that must synchronize internal andexternal clocking signals.

[0035] The memory device 800 includes an address register 802 thatreceives row, column, and bank addresses over an address bus ADDR, witha memory controller (not shown) typically supplying the addresses. Theaddress register 802 receives a row address and a bank address that areapplied to a row address multiplexer 804 and bank control logic circuit806, respectively. The row address multiplexer 804 applies either therow address received from the address register 802 or a refresh rowaddress from a refresh counter 808 to a plurality of row address latchand decoders 810A-D. The bank control logic 806 activates the rowaddress latch and decoder 810A-D corresponding to either the bankaddress received from the address register 802 or a refresh bank addressfrom the refresh counter 808, and the activated row address latch anddecoder latches and decodes the received row address. In response to thedecoded row address, the activated row address latch and decoder 810A-Dapplies various signals to a corresponding memory bank 812A-D to therebyactivate a row of memory cells corresponding to the decoded row address.Each memory bank 812A-D includes a memory-cell array having a pluralityof memory cells arranged in rows and columns, and the data stored in thememory cells in the activated row is stored in sense amplifiers in thecorresponding memory bank. The row address multiplexer 804 applies therefresh row address from the refresh counter 808 to the decoders 810A-Dand the bank control logic circuit 806 uses the refresh bank addressfrom the refresh counter when the memory device 800 operates in anauto-refresh or self-refresh mode of operation in response to an auto-or self-refresh command being applied to the memory device 800, as willbe appreciated by those skilled in the art.

[0036] A column address is applied on the ADDR bus after the row andbank addresses, and the address register 802 applies the column addressto a column address counter and latch 814 which, in turn, latches thecolumn address and applies the latched column address to a plurality ofcolumn decoders 816A-D. The bank control logic 806 activates the columndecoder 816A-D corresponding to the received bank address, and theactivated column decoder decodes the applied column address. Dependingon the operating mode of the memory device 800, the column addresscounter and latch 814 either directly applies the latched column addressto the decoders 816A-D, or applies a sequence of column addresses to thedecoders starting at the column address provided by the address register802. In response to the column address from the counter and latch 814,the activated column decoder 816A-D applies decode and control signalsto an I/O gating and data masking circuit 818 which, in turn, accessesmemory cells corresponding to the decoded column address in theactivated row of memory cells in the memory bank 812A-D being accessed.

[0037] During data read operations, data being read from the addressedmemory cells is coupled through the I/O gating and data masking circuit818 to a read latch 820. The I/O gating and data masking circuit 818supplies N bits of data to the read latch 820, which then applies twoN/2 bit words to a multiplexer 822. In the embodiment of FIG. 3, thecircuit 818 provides 64 bits to the read latch 820 which, in turn,provides two 32 bits words to the multiplexer 822. A data driver 824sequentially receives the N/2 bit words from the multiplexer 822 andalso receives a data strobe signal DQS from a strobe signal generator826 and a delayed clock signal CLKDEL from the delay-locked loop300/500. The DQS signal is used by an external circuit such as a memorycontroller (not shown) in latching data from the memory device 800during read operations. In response to the delayed clock signal CLKDEL,the data driver 824 sequentially outputs the received N/2 bits words asa corresponding data word DQ, each data word being output in synchronismwith a rising or falling edge of a CLK signal that is applied to clockthe memory device 800. The data driver 824 also outputs the data strobesignal DQS having rising and falling edges in synchronism with risingand falling edges of the CLK signal, respectively. Each data word DQ andthe data strobe signal DQS collectively define a data bus DATA. As willbe appreciated by those skilled in the art, the CLKDEL signal from theDLL is a delayed version of the CLK signal, and the delay-locked loop300/500 adjusts the delay of the CLKDEL signal relative to the CLKsignal to ensure that the DQS signal and the DQ words are placed on theDATA bus in synchronism with the CLK signal, as previously describedwith reference to FIGS. 3-6. The DATA bus also includes masking signalsDM0-M, which will be described in more detail below with reference todata write operations.

[0038] During data write operations, an external circuit such as amemory controller (not shown) applies N/2 bit data words DQ, the strobesignal DQS, and corresponding data masking signals DM0-X on the data busDATA. A data receiver 828 receives each DQ word and the associated DM0-Xsignals, and applies these signals to input registers 830 that areclocked by the DQS signal. In response to a rising edge of the DQSsignal, the input registers 830 latch a first N/2 bit DQ word and theassociated DM0-X signals, and in response to a falling edge of the DQSsignal the input registers latch the second N/2 bit DQ word andassociated DM0-X signals. The input register 830 provides the twolatched N/2 bit DQ words as an N-bit word to a write FIFO and driver832, which clocks the applied DQ word and DM0-X signals into the writeFIFO and driver in response to the DQS signal. The DQ word is clockedout of the write FIFO and driver 832 in response to the CLK signal, andis applied to the I/O gating and masking circuit 818. The I/O gating andmasking circuit 818 transfers the DQ word to the addressed memory cellsin the accessed bank 812A-D subject to the DM0-X signals, which may beused to selectively mask bits or groups of bits in the DQ words (i.e.,in the write data) being written to the addressed memory cells.

[0039] A control logic and command decoder 834 receives a plurality ofcommand and clocking signals over a control bus CONT, typically from anexternal circuit such as a memory controller (not shown). The commandsignals include a chip select signal CS*, a write enable signal WE*, acolumn address strobe signal CAS*, and a row address strobe signal RAS*,while the clocking signals include a clock enable signal CKE* andcomplementary clock signals CLK, CLK*, with the “*” designating a signalas being active low. The command signals CS*, WE*, CAS*, and RAS* aredriven to values corresponding to a particular command, such as a read,write, or auto-refresh command. In response to the clock signals CLK,CLK*, the command decoder 834 latches and decodes an applied command,and generates a sequence of clocking and control signals that controlthe components 802-832 to execute the function of the applied command.The clock enable signal CKE enables clocking of the command decoder 834by the clock signals CLK, CLK*. The command decoder 834 latches commandand address signals at positive edges of the CLK, CLK* signals (i.e.,the crossing point of CLK going high and CLK* going low), while theinput registers 830 and data drivers 824 transfer data into and from,respectively, the memory device 800 in response to both edges of thedata strobe signal DQS and thus at double the frequency of the clocksignals CLK, CLK*. This is true because the DQS signal has the samefrequency as the CLK, CLK* signals. The memory device 800 is referred toas a double-data-rate device because the data words DQ being transferredto and from the device are transferred at double the rate of aconventional SDRAM, which transfers data at a rate corresponding to thefrequency of the applied clock signal. The detailed operation of thecontrol logic and command decoder 834 in generating the control andtiming signals is conventional, and thus, for the sake of brevity, willnot be described in more detail.

[0040]FIG. 9 is a block diagram of a computer system 900 includingcomputer circuitry 902 including the memory device 800 of FIG. 8.Typically, the computer circuitry 902 is coupled through address, data,and control buses to the memory device 800 to provide for writing datato and reading data from the memory device. The computer circuitry 902includes circuitry for performing various computing functions, such asexecuting specific software to perform specific calculations or tasks.In addition, the computer system 900 includes one or more input devices904, such as a keyboard or a mouse, coupled to the computer circuitry902 to allow an operator to interface with the computer system.Typically, the computer system 900 also includes one or more outputdevices 906 coupled to the computer circuitry 902, such as outputdevices typically including a printer and a video terminal. One or moredata storage devices 908 are also typically coupled to the computercircuitry 902 to store data or retrieve data from external storage media(not shown). Examples of typical storage devices 908 include hard andfloppy disks, tape cassettes, compact disk read-only (CD-ROMs) andcompact disk read-write (CD-RW) memories, and digital video disks(DVDs).

[0041] It is to be understood that even though various embodiments andadvantages of the present invention have been set forth in the foregoingdescription, the above disclosure is illustrative only, and changes maybe made in detail, and yet remain within the broad principles of theinvention. For example, many of the components described above may beimplemented using either digital or analog circuitry, or a combinationof both, and also, where appropriate, may be realized through softwareexecuting on suitable processing circuitry. Therefore, the presentinvention is to be limited only by the appended claims.

1. A delay-locked loop, comprising: a clock multiplier that generates amultiplied clock signal responsive to an input clock signal, themultiplied clock signal having a frequency that is a multiple of afrequency of the input clock signal; a variable delay circuit coupled tothe clock multiplier and operable to generate a delayed clock signalresponsive to the multiplied clock signal, the delayed clock signalhaving a delay relative to the multiplied clock signal and the variabledelay circuit controlling the value of the delay responsive to a delaycontrol signal; and a comparison circuit coupled to the clock multiplierand to the variable delay circuit, the comparison circuit operable togenerate the delay control signal in response to the relative phases ofthe delayed clock signal and the multiplied clock signal.
 2. The delaylocked loop of claim 1 wherein frequency of the multiplied clock signalis double the frequency of the input clock signal.
 3. The delay-lockedloop of claim 1 wherein the comparison circuit comprises: a fixed delayline that generates a feedback clock signal in response to the delayedclock signal, the feedback clock signal having a fixed delay relative tothe delayed clock signal; and a phase detection circuit coupled toreceive the feedback clock signal and the multiplied clock signal andoperable to develop the delay control signal responsive to the relativephases of the feedback and multiplied clock signals.
 4. The delay-lockedloop of claim 3 wherein the fixed delay line comprises a first delay anda second delay, the first delay including a delay of the clockmultiplier circuit, and the second delay including a delay of an outputcircuit that provides a synchronized clock signal responsive to thedelayed clock signal, the synchronized clock signal having at least sometransitions that occur in synchronism with transitions of the inputclock signal.
 5. The delay-locked loop of claim 4 wherein the phasedetection circuit comprises a phase detector coupled to receive thefeedback clock signal and a delay controller coupled to the phasedetector.
 6. The delay-locked loop of claim 1 wherein the comparisoncircuit detects a phase difference between rising-edges of the delayedclock signal and the multiplied clock signal.
 7. The delay-locked loopof claim 1 wherein the variable delay circuit further comprises: a clockdivider that generates a divided clock signal responsive to the delayedclock signal, the divided clock signal having a frequency that is asub-multiple of a frequency of the delayed clock signal; and a phasedetection and correction circuit coupled to receive the divided clocksignal and the input clock signal, the circuit operable to detect aphase difference between the two clock signals, and operable in a firstmode when the detected phase equals approximately 180 degrees togenerate a synchronized clock signal that is inverted relative to thedivided clock signal, and operable in a second mode to provide thedivided clock signal as the synchronized clock signal.
 8. Thedelay-locked loop of claim 7 wherein the clock divider comprises aD-type flip flop.
 9. A delay-locked loop, comprising: a variable delaycircuit adapted to receive an input clock signal and operable togenerate a delayed clock signal responsive to the input clock signal,the delayed clock signal having a delay relative to the input clocksignal and the variable delay circuit controlling the value of the delayresponsive to a delay control signal; and a comparison circuit coupledto the variable delay circuit, the comparison circuit operable togenerate the delay control signal in response to the relative phases ofthe rising-edge transitions of the delayed and input clock signals andin response to the relative phases of the falling-edge transitions ofthe delayed and input clock signals.
 10. The delay-locked loop of claim9 wherein the comparison circuit comprises: a fixed delay line thatgenerates a feedback clock signal in response to the delayed clocksignal, the feedback clock signal having a fixed delay relative to thedelayed clock signal; a rising-edge phase detector coupled to receivethe feedback clock signal and the input clock signal, and operable togenerate a rising-edge delay control signal responsive to a detectedphase between rising-edges of the feedback and input clock signals; afalling-edge phase detector coupled to receive the feedback clock signaland the input clock signal, and operable to generate a falling-edgedelay control signal responsive to a detected phase betweenfalling-edges of the feedback and input clock signals; and a delaycontroller coupled to the phase detectors and operable to develop thedelay control signal responsive to the rising- and falling-edge delaycontrol signals.
 11. The delay-locked loop of claim 10 wherein the fixeddelay comprises a first delay and a second delay, the first delayincluding an input buffer, and the second delay including a delay of anoutput circuit that provides a synchronized clock signal responsive tothe delayed clock signal, the synchronized clock signal beingsynchronized with the input clock signal.
 12. The delay-locked loop ofclaim 11 wherein the output circuit comprises a data output buffer. 13.A delay-locked loop, comprising: a clock multiplier adapted to receivean input clock signal and operable to generate a multiplied clock signalresponsive to the input clock signal, the multiplied clock signal havinga frequency that is a multiple of the frequency of the input clocksignal; a variable delay circuit coupled to the clock multiplier circuitand operable to generate a delayed clock signal responsive to themultiplied clock signal, the delayed clock signal having a delayrelative to the multiplied clock signal and the variable delay circuitoperable to control the value of the delay responsive to a delay controlsignal; and a feedback delay circuit coupled to the variable delaycircuit, the feedback delay circuit generating a feedback clock signalresponsive to the delayed clock signal, the feedback clock signal havinga model delay relative to the delayed clock signal; a phase detectorcoupled to the clock multiplier to receive the multiplied clock signaland coupled to the variable delay circuit, the phase detector generatingthe delay control signal in response to the relative phases of thedelayed clock signal and the multiplied clock signal.
 14. The delaylocked loop of claim 13 wherein frequency of the multiplied clock signalis double the frequency of the input clock signal.
 15. The delay-lockedloop of claim 13 wherein the fixed delay circuit comprises a first delayand a second delay, the first delay including a delay of the clockmultiplier, and the second delay including a delay of an output circuitthat provides a synchronized clock signal responsive to the delayedclock signal, the synchronized clock signal having at least sometransitions that occur in synchronism with transitions of the inputclock signal.
 16. The delay-locked loop of claim 13 wherein the phasedetector comprises a phase detection circuit coupled to receive thefeedback clock signal and a delay controller coupled to the phasedetector and the variable delay circuit.
 17. The delay-locked loop ofclaim 13 wherein the variable delay circuit further comprises: a clockdivider that generates a divided clock signal responsive to the delayedclock signal, the divided clock signal having a frequency that is asub-multiple of a frequency of the delayed clock signal; and a phasedetection and correction circuit coupled to receive the divided clocksignal and the input clock signal, the circuit operable to detect aphase difference between the two clock signals, and operable in a firstmode when the detected phase equals approximately 180 degrees togenerate a synchronized clock signal that is inverted relative to thedivided clock signal, and operable in a second mode to provide thedivided clock signal as the synchronized clock signal.
 18. Thedelay-locked loop of claim 17 wherein the clock divider comprises aD-type flip flop.
 19. A delay-locked loop, comprising: a variable delaycircuit adapted to receive an input clock signal and operable togenerate a delayed clock signal responsive to the input clock signal,the delayed clock signal having a delay relative to the input clocksignal and the variable delay circuit operable to control the value ofthe delay responsive to a delay control signal; and a feedback delaycircuit coupled to the variable delay circuit, the feedback delaycircuit generating a feedback clock signal responsive to the delayedclock signal, the feedback clock signal having a model delay relative tothe delayed clock signal; a rising-edge phase detector adapted toreceive the input clock signal and coupled to the variable delay circuitto receive the delayed clock signal, the rising-edge phase detectorgenerating the delay control signal in response to the relative phasesof rising-edges of the delayed clock signal and the input clock signal;and a falling-edge phase detector adapted to receive the input clocksignal and coupled to the variable delay circuit to receive the delayedclock signal, the falling-edge phase detector generating the delaycontrol signal in response to the relative phases of falling-edges ofthe delayed clock signal and the input clock signal.
 20. Thedelay-locked loop of claim 19 wherein the model delay of the feedbackclock signal corresponds to a first delay component corresponding to aninput buffer adapted receive an external clock signal and to develop theinput clock signal to the variable delay circuit in response to theexternal clock signal, and a second delay component corresponding to anoutput buffer that receives the delayed clock signal and generates asynchronized clock signal in response the delayed clock signal, thesynchronized clock signal being synchronized with the external clocksignal when the delay-locked loop is locked.
 21. A delay-locked loop,comprising: an input buffer adapted to receive an input clock signal andoperable to generate a buffered clock signal responsive to the inputclock signal; a clock multiplier coupled to the input buffer andoperable to generate a multiplied clock signal responsive to thebuffered clock signal, the multiplied clock signal having a frequencythat is a multiple of the frequency of the buffered clock signal; avariable delay line coupled to the clock multiplier and operable togenerate a delayed clock signal responsive to the multiplied clocksignal, the delayed clock signal having a delay relative to themultiplied clock signal and the variable delay line operable to controlthe value of the delay responsive to a delay control signal; and afeedback delay line coupled to the variable delay line, the feedbackdelay line generating a feedback clock signal responsive to the delayedclock signal, the feedback clock signal having a model delay relative tothe delayed clock signal; a phase detector coupled to the clockmultiplier to receive the multiplied clock signal and coupled to thefeedback delay line to receive the feedback clock signal, the phasedetector generating the delay control signal in response to the relativephases of the buffered and feedback clock signals; a clock dividercoupled to the variable delay line to receive the delayed clock signal,and operable to generate a divided clock signal responsive to thedelayed clock signal, the divided clock signal having a frequency thatis a sub-multiple of a frequency of the delayed clock signal; a phasedetection and correction circuit coupled to the clock divider to receivethe divided clock signal and adapted to receive the input clock signal,the circuit operable to detect a phase difference between the two clocksignals, and operable in a first mode when detected phase equalsapproximately 180 degrees to generate an output clock signal that isinverted relative to the divided clock signal, and operable in a secondmode to provide the divided clock signal as the output clock signal; andan output buffer coupled to the phase correction and detection circuitand operable to generate a synchronized clock signal in response to theoutput clock signal.
 22. The delay-locked loop of claim 21 wherein themodel delay of the feedback delay line comprises a first delaycorresponding to delays of the clock multiplier and input buffer, and asecond component corresponding to delays of the clock divider, phasedetection and correction circuit, and output buffer.
 23. Thedelay-locked loop of claim 21 wherein the clock multiplier circuitgenerates the multiplied clock signal have a frequency of twice thefrequency of the input clock signal.
 24. The delay-locked loop of claim21 wherein the phase detector detects the relative phases of thebuffered and feedback clock signals in response to rising-edges of thesesignals.
 25. The delay-locked loop of claim 21 wherein the clock dividercomprises a D-type flip flop.
 26. The delay-locked loop of claim 21wherein the clock multiplier comprises an XOR gate having a first inputadapted to receive the input clock signal, and a second input thatreceives the input clock signal through a delay circuit, the XOR gategenerating the multiplied clock signal on an output in response to thesignals applied to the first and second inputs.
 27. The delay-lockedloop of claim 21 wherein the output buffer is adapted to receive a datasignal and provides the data signal on an output as the synchronizedclock signal in response to the output clock signal.
 28. A delay-lockedloop, comprising an input buffer circuit adapted to receive an inputclock signal and operable to generate a buffered clock in response tothe input clock signal; a variable delay line coupled to the inputbuffer and operable to generate a delayed clock signal responsive to thebuffered clock signal, the delayed clock signal having a delay relativeto the buffered clock signal and the variable delay line operable tocontrol the value of the delay responsive to a delay control signal; afeedback delay line coupled to the variable delay line, the feedbackdelay line generating a feedback clock signal responsive to the delayedclock signal, the feedback clock signal having a model delay relative tothe delayed clock signal; a rising-edge phase detector coupled to theinput buffer to receive the buffered clock signal and coupled to thevariable delay line to receive the delayed clock signal, the rising-edgephase detector generating the delay control signal in response to therelative phases of rising-edges of the delayed clock signal and thebuffered clock signal; a falling-edge phase detector adapted to receivethe input clock signal and coupled to the variable delay line to receivethe delayed clock signal, the falling-edge phase detector generating thedelay control signal in response to the relative phases of falling-edgesof the delayed clock signal and the buffered clock signal; an outputbuffer coupled to the variable delay line to receive the delayed clocksignal, the output buffer circuit generating a synchronized clock signalin response to the delayed clock signal.
 29. The delay-locked loop ofclaim 28 wherein the model delay of the feedback delay line comprises afirst delay corresponding to delay of the input buffer, and a secondcomponent corresponding to a delay of the output buffer.
 30. Thedelay-locked loop of claim 28 wherein the output buffer is adapted toreceive a data signal and provides the data signal on an output as thesynchronized clock signal in response to the delayed clock signal.
 31. Amemory device, comprising: an address bus; a control bus; a data bus; anaddress decoder coupled to the address bus; a read/write circuit coupledto the data bus; a control circuit coupled to the control bus; amemory-cell array coupled to the address decoder, control circuit, andread/write circuit; and a delay-locked loop coupled to at least thecontrol circuit and adapted to receive an input clock signal, thedelay-locked loop operable to generate a delayed clock signal and thecontrol circuit generating control signals in response to the delayedclock signal, the delay-locked loop comprising, a clock multiplier thatgenerates a multiplied clock signal responsive to the input clocksignal, the multiplied clock signal having a frequency that is amultiple of a frequency of the input clock signal; a variable delaycircuit coupled to the clock multiplier and operable to generate thedelayed clock signal responsive to the multiplied clock signal, thedelayed clock signal having a delay relative to the multiplied clocksignal and the variable delay circuit controlling the value of the delayresponsive to a delay control signal; and a comparison circuit coupledto the clock multiplier and to the variable delay circuit, thecomparison circuit operable to generate the delay control signal inresponse to the relative phases of the delayed clock signal and themultiplied clock signal.
 32. The memory device of claim 31 wherein thememory device comprises a DDR SDRAM and the delayed clock signal isapplied to clock an output driver coupled to the data bus.
 33. A memorydevice, comprising: an address bus; a control bus; a data bus; anaddress decoder coupled to the address bus; a read/write circuit coupledto the data bus; a control circuit coupled to the control bus; amemory-cell array coupled to the address decoder, control circuit, andread/write circuit; a delay-locked loop coupled to at least the controlcircuit and adapted to receive an input clock signal, the delay-lockedloop operable to generate a delayed clock signal and the control circuitgenerating control signals in response to the delayed clock signal, thedelay-locked loop comprising, a variable delay circuit coupled to theinput clock signal and operable to generate the delayed clock signalresponsive to the input clock signal, the delayed clock signal having adelay relative to the input clock signal and the variable delay circuitcontrolling the value of the delay responsive to a delay control signal;and a comparison circuit coupled to the variable delay circuit, thecomparison circuit operable to generate the delay control signal inresponse to the relative phases of the rising-edge transitions of thedelayed and input clock signals and in response to the relative phasesof the falling-edge transitions of the delayed and input clock signals.34. The memory device of claim 33 wherein the memory device comprises aDDR SDRAM and the delayed clock signal is applied to clock an outputdriver coupled to the data bus.
 35. A computer system, comprising: adata input device; a data output device; a processor coupled to the datainput and output devices; and a memory device coupled to the processor,the memory device comprising, an address bus; a control bus; a data bus;an address decoder coupled to the address bus; a read/write circuitcoupled to the data bus; a control circuit coupled to the control bus; amemory-cell array coupled to the address decoder, control circuit, andread/write circuit; and a delay-locked loop coupled to at least thecontrol circuit and adapted to receive an input clock signal, thedelay-locked loop operable to generate a delayed clock signal and thecontrol circuit generating control signals in response to the delayedclock signal, the delay-locked loop comprising, a clock multiplier thatgenerates a multiplied clock signal responsive to the input clocksignal, the multiplied clock signal having a frequency that is amultiple of a frequency of the input clock signal; a variable delaycircuit coupled to the clock multiplier and operable to generate thedelayed clock signal responsive to the multiplied clock signal, thedelayed clock signal having a delay relative to the multiplied clocksignal and the variable delay circuit controlling the value of the delayresponsive to a delay control signal; and a comparison circuit coupledto the clock multiplier and to the variable delay circuit, thecomparison circuit operable to generate the delay control signal inresponse to the relative phases of the delayed clock signal and themultiplied clock signal.
 36. The memory device of claim 35 wherein thememory device comprises a DDR SDRAM and the delayed clock signal isapplied to clock an output driver coupled to the data bus.
 37. Acomputer system, comprising: a data input device; a data output device;a processor coupled to the data input and output devices; and a memorydevice coupled to the processor, the memory device comprising, anaddress bus; a control bus; a data bus; an address decoder coupled tothe address bus; a read/write circuit coupled to the data bus; a controlcircuit coupled to the control bus; a memory-cell array coupled to theaddress decoder, control circuit, and read/write circuit; a delay-lockedloop coupled to at least the control circuit and adapted to receive aninput clock signal, the delay-locked loop operable to generate a delayedclock signal and the control circuit generating control signals inresponse to the delayed clock signal, the delay-locked loop comprising,a variable delay circuit coupled to the input clock signal and operableto generate the delayed clock signal responsive to the input clocksignal, the delayed clock signal having a delay relative to the inputclock signal and the variable delay circuit controlling the value of thedelay responsive to a delay control signal; and a comparison circuitcoupled to the variable delay circuit, the comparison circuit operableto generate the delay control signal in response to the relative phasesof the rising-edge transitions of the delayed and input clock signalsand in response to the relative phases of the falling-edge transitionsof the delayed and input clock signals.
 38. The memory device of claim37 wherein the memory device comprises a DDR SDRAM and the delayed clocksignal is applied to clock an output driver coupled to the data bus. 39.A method for generating a delayed clock signal having a delay relativeto an applied clock signal, the method comprising: generating amultiplied clock signal having a frequency that is a multiple of theapplied clock signal; generating the delayed clock signal in response tothe multiplied clock signal; delaying the delayed clock signal relativeto the multiplied clock signal; detecting a phase difference between themultiplied clock signal and the delayed clock signal; and adjusting thedelay of the delayed clock signal responsive to the detected phasedifference.
 40. The method of claim 39 wherein generating a multipliedclock signal comprises generating a clock signal having a frequency that2^ N times the frequency of the applied clock signal, where N is apositive integer.
 41. The method of claim 39 wherein N=1 and themultiplied clock signal is twice the frequency of the applied clocksignal.
 42. The method of claim 39 wherein detecting a phase differencebetween the multiplied clock signal and the delayed clock signalcomprises delaying the delayed clock signal by a model delay to generatea feedback clock signal, and detecting the phase difference between thefeedback clock signal and the multiplied clock signal.
 43. The method ofclaim 39 further comprising clocking data in response to the delayedclock signal.
 44. A method for generating a delayed clock signal havinga delay relative to an applied clock signal, the method comprising:generating the delayed clock signal in response to the applied clocksignal; delaying the delayed clock signal relative to the applied clocksignal; detecting a phase difference between rising edges of the delayedclock signal and rising-edges of the applied clock signal; detecting aphase difference between falling edges of the delayed clock signal andfalling edges of the applied clock signal; and adjusting the delay ofthe delayed clock signal responsive to the detected phase differences.45. The method of claim 44 wherein detecting a phase difference betweenrising edges of the delayed clock signal and rising-edges of the appliedclock signal comprises delaying the delayed clock signal by a modeldelay to generate a feedback clock signal, and detecting the phasedifference between rising-edges of the feedback clock signal and theapplied clock signal, and wherein detecting a phase difference betweenfalling edges of the delayed clock signal and falling edges of theapplied clock signal comprises detecting the phase differencefalling-edges of the feedback clock signal and the applied clock signal.46. The method of claim 44 further comprising clocking data in responseto the delayed clock signal.